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HDL design

COURSE: HDL design

Code: ФЕИТ07009

ECTS points: 6 ECTS

Number of classes per week: 3+0+0+3

Lecturer: prof. Marija Kalendar

Subject of the course content: Hardware description languages (Verilog HDL, VHDL, SystemC). Systems for generating HDL from C and Matlab. Design verification and testability of embedded systems. Software platforms for simulating and testing digital systems.

Dedicated computer systems and IP-cores. Using IP-cores for dedicated computer systems design and implementation.

System-on-chip design with HDL. Description of processors in HDL. Description of busses in HDL.

Energy-efficient embedded systems design. Design of communication for embedded computer systems.

Literature:

  1. P. Mishra, N. Dutt, "Processor Description Languages", Morgan Kauffman, 2007
  2. D. Perry, "VHDL: Programming by Example, 4th Edition", McGraw Hill, 2002
  3. P. Chu, "RTL Hardware Design Using VHDL", John Wiley, 2006